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? 2014 microchip technology inc. ds00001716a-page 1 datasheet product features USB4604 usb 2.0 hsic hi-speed 4-port hub controller highlights ? hub controller ic with 4 downstream ports ? high-speed inter-chip (hsic) support ? upstream port selectable between hsic or usb 2.0 ? usb-if battery charger revision 1.2 support on up & downstream ports (dcp, cdp, sdp) ? battery charging support for apple ? devices ? flexconnect : downstream port 1 able to swap with upstream port, allowing mast er capable devices to control other devices on the hub ? usb to i 2 c tm /spi bridge endpoint support ? usb link power management (lpm) support ? suspend pin for remote wakeup indication to host ? start of frame (sof) synchronized clock output pin ? vendor specific messaging (vsm) support ? enhanced oem configuration options available through otp or smbus slave port ? flexible power rail support ? vbus or vbat only operation ? 3.3v only operation ? vbat + 1.8v operation ? 3.3v + 1.8v operation ? 48-pin (7x7mm) sqfn, rohs compliant package target applications ? lcd monitors and tvs ? multi-function usb peripherals ? pc mother boards ? set-top boxes, dvd players, dvr/pvr ? printers and scanners ? pc media drive bay ? portable hub boxes ? mobile pc docking ? embedded systems additional features ? multitrak tm ? dedicated transaction translator per port ? portmap ? configurable port mapping and disable sequencing ? portswap ? configurable differential intra-pair signal swapping ? phyboost tm ? programmable usb transceiver drive strength for recovering signal integrity ? varisense tm ? programmable usb receiver sensitivity ? low power operation ? full power management with individual or ganged power control of each downstream port ? built-in self-powered or bus-powered internal default settings provide flexibility in the quantity of usb expansion ports utilized without redesign ? supports ?quad page? configuration otp flash ? four consecutive 200 byte configuration pages ? fully integrated usb termination and pull-up/pull- down resistors ? on-chip power on reset (por) ? internal 3.3v and 1.2v voltage regulators ? on board 24mhz crystal driver, resonator, or external 24mhz clock input ? usb host/device speed indicator. per-port 3-color led drivers indicate the speed of usb host and device connection - hi-speed (480 mbps), full-speed (12 mbps), low-speed (1.5 mbps) ? environmental ? commercial temperature range support (0oc to 70oc) ? industrial temperature range support (-40oc to 85oc)
order number(s): this product meets the halogen maximum concentration values per iec61249-2-21 the table above represents valid part numbers at the time of printing and may not represent parts that are currently available. for the latest list of valid ordering numbers for this product, please contact the nearest sales office. order number temperature range package type USB4604-1080hn (hub co ntroller enabled) 0c to +70c 48-pin sqfn USB4604-1070hn (hub controller disabled) USB4604-1080hn-tr (hub controller enabled) 0c to +70c 48-pin sqfn (tape & reel) USB4604-1070hn-tr (hub controller disabled) USB4604i-1080hn (hub controller enabled) -40c to +85c 48-pin sqfn USB4604i-1070hn (hub controller disabled) USB4604i-1080hn-tr (hub controller enabled) -40c to +85c 48-pin sqfn (tape & reel) USB4604i-1070hn-tr (hub controller disabled) usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 2 ? 2014 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensur e successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/documentat ion issues become known to us, we will publish an errata shee t. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 3 table of contents chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 2 acronyms and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chapter 3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 buffer type descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chapter 4 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4.1 integrated power regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.1 3.3v regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.2 1.2v regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 power configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 single supply configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.2 dual supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 power connection diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 5.1 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.2 hardware initialization stage (hw_init ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.3 software initialization stage (sw_in it) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 5.1.4 soc configuration stage (soc_cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.5 configuration stage (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.6 battery charger detection stage (chgdet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.7 hub connect stage (hub.connect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.8 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 chapter 6 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 6.1 configuration method selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 customer accessible functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.1 usb accessible functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.2 smbus accessible functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 device configuration straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 port disable (prt_dis_mx/prt_dis_px) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.2 spi speed select (spi_spd _sel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 chapter 7 device interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.1 operation of the hi-speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.2 operation of the dual high speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.3 32 byte cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.4 interface operation to the spi port when not pe rforming fast reads. . . . . . . . . . . . . . . . . 35 7.1.5 erase example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 4 ? 2014 microchip technology inc. 7.1.6 byte program example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1.7 command only program example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1.8 jedec-id read example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 i2c master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.1 i2c message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.2 pull-up resistors for i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 smbus slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 chapter 8 functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 battery charger detection & charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.1 upstream battery charger detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 8.1.2 downstream battery charging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 sof clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3 flex connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.1 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4.2 external chip reset (reset_n). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4.3 usb bus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.5 link power management (lpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.6 suspend (suspend) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 9 operational char acteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1 absolute maximum ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2 operating conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.1 operational / unconfigured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.2 suspend / standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.4 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.5 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.5.1 power-on configuration strap valid timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.5.2 reset and configuration strap timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 9.5.3 usb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.5.4 hsic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.5.5 smbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.5.6 i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.5.7 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.6 clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.6.1 oscillator/crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.6.2 external reference clock (refclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 chapter 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 11 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 5 list of figures figure 1.1 system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3.1 48-sqfn pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4.1 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5.1 hub operational mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7.1 spi hi-speed read sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7.2 spi dual hi-speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7.3 spi erase sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 7.4 spi byte program sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 7.5 spi command only sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7.6 spi jedec-id read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 7.7 i2c sequential access write format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 7.8 i2c sequential access read format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 8.1 battery charging external power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 8.2 sof output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 9.1 single/dual supply rise time models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 9.1 power-on configuration strap valid timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 9.2 reset_n configurat ion strap timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 9.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 10.1 48-sqfn package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 6 ? 2014 microchip technology inc. list of tables table 3.1 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.2 48-sqfn package pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3.3 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6.1 prt_dis_mx/prt_dis_px configurat ion definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 6.2 spi_spd_sel configuration definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8.1 chargers compatible with upstream detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.2 downstream port types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8.3 lpm state definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 9.1 operational/unconfigured power consumption (hsi c upstream) . . . . . . . . . . . . . . . . . . . . . 50 table 9.2 operational/unconfigured power consumption (usb upstream) . . . . . . . . . . . . . . . . . . . . . . 50 table 9.3 single supply suspend/standby power consumptio n (usb upstream). . . . . . . . . . . . . . . . . 51 table 9.4 single supply suspend/standby power consumptio n (hsic upstream) . . . . . . . . . . . . . . . . 51 table 9.5 dual supply suspend/standb y power consumption (usb upstream) . . . . . . . . . . . . . . . . . . 52 table 9.6 dual supply suspend/standb y power consumption (usb upstream) . . . . . . . . . . . . . . . . . . 52 table 9.7 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 9.8 power-on configuration st rap valid timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 table 9.9 reset_n configuration st rap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 9.10 spi timing values (30 mhz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 9.11 spi timing values (60 mhz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 9.12 crystal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 11.1 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 7 chapter 1 general description the USB4604 is a low-power, oem configurable, mtt (multi-transaction translator) usb 2.0 hub controller with 4 downstream ports and advanced features for embedded usb applications. the USB4604 is fully compliant with the usb 2.0 specification, usb 2.0 link power management addendum, high-speed inter-chip (hsic) usb electrical specification revision 1.0, and will attach to an upstream port as a full-speed hub or as a full-/hi-speed hub. the 4-port hub supports low-speed, full-speed, and hi-speed (if operating as a hi-spe ed hub) downstream devices on all of the enabled downstream (non-hsic) ports. hsic ports support only hi-speed operation. the USB4604 has been specifically optimized fo r embedded systems where high performance, and minimal bom costs are critical design requirements. standby mode power has been minimized and reference clock inputs can be aligned to the customer?s specific application. flexible power rail options ease integration into energy efficient designs by allowing the USB4604 to be powered in a single- source (vbus, vbat, 3.3v) or a dual-source (vbat + 1.8, 3.3v + 1.8) configuration. additionally, all required resistors on the usb ports are integrated into the hub, including all series termination and pull-up/pull-down resistors on the d+ and d? pins. the USB4604 supports both upstream battery charger detection and downstream battery charging. the USB4604 integrated battery ch arger detection circuitry supports the usb-if battery charging (bc1.2) detection method and most apple devices. th ese circuits are used to detect the attachment and type of a usb charger and provide an interrupt out put to indicate charger information is available to be read from the device?s status registers via t he serial interface. the u sb4604 provides the battery charging handshake and supports the foll owing usb-if bc1.2 charging profiles: ? dcp: dedicated charging port (power brick with no data) ? cdp: charging downstream port (1.5a with data) ? sdp: standard downstream port (0.5a with data) ? custom profiles loaded via smbus or otp the USB4604 provides an additional usb endpoint dedicated for use as a usb to i 2 c/spi interface, allowing external circuits or devices to be monitore d, controlled, or configured via the usb interface. additionally, the USB4604 includes many po werful and unique features such as: flexconnect , which provides flexible connectivity options. the USB4604?s downstream port 1 can be swapped with the upstream port, allowing master capa ble devices to control other devices on the hub. multitrak tm technology , which utilizes a dedicated transaction translator (tt) per port to maintain consistent full-speed data throughput regardless of the number of active downstream connections. multitrak tm outperforms conventional usb 2.0 hubs with a si ngle tt in usb full-speed data transfers. portmap , which provides flexible port mapping and disable sequences. the downstream ports of a USB4604 hub can be reordered or disabled in any sequence to support multiple platform designs with minimum effort. for any port that is disabled, the USB4604 hub controllers aut omatically reorder the remaining ports to match the usb host controller?s port numbering scheme. portswap , which adds per-port programmability to usb differential-pair pin locations. portswap allows direct alignment of usb signals (d+/d-) to connectors to avoid uneven trace length or crossing of the usb differential signals on the pcb. phyboost , which provides programmable levels of hi-speed usb signal drive strength in the downst ream port transceivers. phyboost attempts to restore usb signal integrity in a compromised system environment. the graphic on the right shows an example of hi- speed usb eye diagrams before and after phyboost signal integrity restoration. varisense , which controls the usb receiver sensitivit y enabling programmable levels of usb signal receive sensitivity. this capabilit y allows operation in a sub-optima l system environment, such as when a captive usb cable is used.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 8 ? 2014 microchip technology inc. the USB4604 is available in commercial (0c to +7 0c) and industrial (-40c to +85c) temperature range versions. as shown in the ordering code matrix, two USB4604 firmware revisions are available: ?-1080? and ?- 1070?. the -1080 version enables the internal hub cont roller, while the -1070 version disables it. there are no additional differences between these two versions. the hub controller adds advanced functionality to the USB4604 by enabling the host to send commands directly to it via the upstream usb c onnection. commands to the hub controller must be sent to the virtual 5th port in the hub. the follo wing functions can be controlled via commands through the hub controller: ? usb to smbus bridging: the host can send co mmands through usb to any device connected to the hub through the smbus. ? usb to uart bridging: the host can send commands through sub to any device connected to the hub through the uart. ? gpio control: the gpios on the hub can be dy namically configured and controlled by the host. ? otp programming: permanent customer confi gurations can be loaded to the one time programmable memory.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 9 1.1 block diagram figure 1.1 details the internal block diagram of the USB4604. figure 1.1 system block diagram repeater controller sie serial interface to i 2 c master/slave routing & port re-ordering logic scl sda port controller vddcr12 tt #3 tt #2 tt #1 1.2v reg reset_n vddcorereg tt #4 gpio port power ocs tt #5 udc 20 2kb dp sram 8051 controller spi spi/i2c gpio bridge 4kb sram 32kb rom 2kb otp 256b iram vdda33 vbat 3.3v reg swap phy usb down or upstream phy usb downstream phy usb downstream phy usb downstream flex phy up or downstream hsic/usb flex hsic vdd33
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 10 ? 2014 microchip technology inc. chapter 2 acronyms and definitions 2.1 acronyms eop: end of packet ep: endpoint fs: full-speed gpio: general purpose i/o (that is input/output to/from the device) hs: hi-speed hsos: high speed over sampling hsic: high-speed inter-chip i 2 c ? : inter-integrated circuit ls: low-speed otp: one time programmable pcb: printed circuit board pcs: physical coding sublayer phy: physical layer smbus: system management bus uuid: universally unique identification 2.2 reference documents 1. unicode utf-16le for string descriptors usb engineering change notice, december 29th, 2004, http://www.usb.org 2. universal serial bus specification , revision 2.0, april 27th, 2000, http://www.usb.org 3. battery charging specification , revision 1.2, dec. 07, 2010, http://www.usb.org 4. high-speed inter-chip usb electrical specification , version 1.0, sept. 23, 2007, http://www.usb.org 5. i 2 c-bus specification , version 1.1, http://www.nxp.com 6. system management bus specification , version 1.0, http://smbus.org/specs
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 11 chapter 3 pin descriptions figure 3.1 48-sqfn pin assignments swap_usbdn1_dm/prt_dis_m1 swap_usbdn1_dp/prt_dis_p1 usbdn2_dm/prt_dis_m2 usbdn2_dp/prt_dis_p2 ground pad (must be connected to vss) 38 39 37 40 vdd12 41 flex_hsic_up_strobe 43 xtal2 44 xtal1/refclk rbias vdda33 vddcorereg flex_hsic_up_data 42 1 2 3 4 5 6 7 8 9 10 11 21 20 19 18 17 16 15 14 13 23 22 24 35 36 33 32 31 30 29 28 34 27 26 25 indicates pins on the bottom of the device. usbdn3_dm/prt_dis_m3 nc nc flex_usbup_dm/prt_dis_m0 flex_usbup_dp/prt_dis_p0 vdd33 reset_n nc scl/smbclk sda/smbdata uart_tx/ocs4_n prtpwr4/prtctl4 vbus_det uart_rx/ocs3_n spi_clk nc prtpwr3/prtctl3 ocs2_n prtpwr2/prtctl2 ocs1_n prtpwr1/prtctl1 spi_di nc sof vddcr12 vdd33 usbdn3_dp/prt_dis_p3 usbdn4_dm/prt_dis_m4 usbdn4_dp/prt_dis_p4 suspend vbat vdda33 12 45 47 48 46 spi_do/spi_spd_sel spi_ce_n vdda33 nc USB4604 (top view)
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 12 ? 2014 microchip technology inc. 3.1 pin descriptions this section provides a detailed description of eac h pin. the signals are arranged in functional groups according to their a ssociated interface. the ?_n? symbol in the signal name indicates that th e active, or asserted, state occurs when the signal is at a low voltage level. for example, reset_n i ndicates that the reset sig nal is active low. when ?_n? is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used exclusively. this is done to avoid confusion when working with a mixture of ?active low? and ?active high? signals. the term asser t, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate, or negation, indicates that a signal is inactive. note: the buffer type for each signal is indi cated in the buffer type column of ta b l e 3 . 1 . a description of the buffer types is provided in section 3.3 . note: compatibility with the ucs100x family of usb port power controllers requires the ucs100x be connected on port 1 of the USB4604. addi tionally, both prtpwr1 and ocs1_n must be pulled high at power-on reset (por). table 3.1 pin descriptions num pins name symbol buffer type description usb/hsic interfaces 1 upstream usb d+ (flex port 0) flex_usbup_dp aio upstream usb port 0 d+ data signal. see note 3.2 . note: the upstream port 0 signals can be optionally swapped with the downstream port 1 signals. port 0 d+ disable configuration strap prt_dis_p0 is this strap is used in conjunction with prt_dis_m0 to disable usb port 0. 0 = port 0 d+ enabled 1 = port 0 d+ disabled note: both prt_dis_p0 and prt_dis_m0 must be tied to vdd33 at reset to place port 0 into hsic mode. see note 3.3 for more information on configuration straps.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 13 1 upstream usb d- (flex port 0) flex_usbup_dm aio upstream usb port 0 d- data signal. see note 3.2 . note: the upstream port 0 signals can be optionally swapped with the downstream port 1 signals. port 0 d- disable configuration strap prt_dis_m0 is this strap is used in conjunction with prt_dis_p0 to disable usb port 0. 0 = port 0 d- enabled 1 = port 0 d- disabled note: both prt_dis_p0 and prt_dis_m0 must be tied to vdd33 at reset to place port 0 into hsic mode. see note 3.3 for more information on configuration straps. 1 upstream hsic data (flex port 0) flex_hsic_up_ data hsic upstream hsic port 0 data signal. see note 3.2 . note: the upstream port 0 signals can be optionally swapped with the downstream port 1 signals. 1 upstream hsic strobe (flex port 0) flex_hsic_up_ strobe hsic upstream hsic po rt 0 strobe signal. see note 3.2 . note: the upstream port 0 signals can be optionally swapped with the downstream port 1 signals. 1 downstream usb d+ (swap port 1) swap_usbdn1_dp aio downstream usb port 1 d+ data signal. note: the downstream port 1 signals can be optionally swapped with the upstream port 0 signals. port 1 d+ disable configuration strap prt_dis_p1 is this strap is used in conjunction with prt_dis_m1 to disable usb port 1. 0 = port 1 d+ enabled 1 = port 1 d+ disabled note: both prt_dis_p1 and prt_dis_m1 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 14 ? 2014 microchip technology inc. 1 downstream usb d- (swap port 1) swap_usbdn1_dm aio downstream usb port 1 d- data signal. note: the downstream port 1 signals can be optionally swapped with the upstream port 0 signals. port 1 d- disable configuration strap prt_dis_m1 is this strap is used in conjunction with prt_dis_p1 to disable usb port 1. 0 = port 1 d- enabled 1 = port 1 d- disabled note: both prt_dis_p1 and prt_dis_m1 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. 1 downstream usb d+ (port 2) usbdn2_dp aio downstream usb port 2 d+ data signal. port 2 d+ disable configuration strap prt_dis_p2 is this strap is used in conjunction with prt_dis_m2 to disable usb port 2. 0 = port 2 d+ enabled 1 = port 2 d+ disabled note: both prt_dis_p2 and prt_dis_m2 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. 1 downstream usb d- (port 2) usbdn2_dm aio downstream usb port 2 d- data signal. port 2 d- disable configuration strap prt_dis_m2 is this strap is used in conjunction with prt_dis_p2 to disable usb port 2. 0 = port 2 d- enabled 1 = port 2 d- disabled note: both prt_dis_p2 and prt_dis_m2 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 15 1 downstream usb d+ (port 3) usbdn3_dp aio downstream usb port 3 d+ data signal. port 3 d+ disable configuration strap prt_dis_p3 is this strap is used in conjunction with prt_dis_m3 to disable usb port 3. 0 = port 3 d+ enabled 1 = port 3 d+ disabled note: both prt_dis_p3 and prt_dis_m3 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. 1 downstream usb d- (port 3) usbdn3_dm aio downstream usb port 3 d- data signal. port 3 d- disable configuration strap prt_dis_m3 is this strap is used in conjunction with prt_dis_p3 to disable usb port 3. 0 = port 3 d- enabled 1 = port 3 d- disabled note: both prt_dis_p3 and prt_dis_m3 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. 1 downstream usb d+ (port 4) usbdn4_dp aio downstream usb port 4 d+ data signal. port 4 d+ disable configuration strap prt_dis_p4 is this strap is used in conjunction with prt_dis_m4 to disable usb port 4. 0 = port 4 d+ enabled 1 = port 4 d+ disabled note: both prt_dis_p4 and prt_dis_m4 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 16 ? 2014 microchip technology inc. 1 downstream usb d- (port 4) usbdn4_dm aio downstream usb port 4 d- data signal. port 4 d- disable configuration strap prt_dis_m4 is this strap is used in conjunction with prt_dis_p4 to disable usb port 4. 0 = port 4 d- enabled 1 = port 4 d- disabled note: both prt_dis_p4 and prt_dis_m4 must be tied to vdd33 at reset to disable the associated port. see note 3.3 for more information on configuration straps. i 2 c/smbus interface 1 i 2 c serial clock input scl i_smb i 2 c serial clock input smbus clock smbclk i_smb smbus serial clock input 1 i 2 c serial data sda is/od8 i 2 c bidirectional serial data smbus serial data smbdata is/od8 smbus bidirectional serial data spi master interface 1 spi chip enable output spi_ce_n o12 active-low spi chip enable output. note: if the spi is enabled, this pin will be driven high in powerdown states. 1 spi clock output spi_clk o12 spi clock output 1 spi data output spi_do o12 spi data output spi speed select configuration strap spi_spd_sel is (pd) this strap is used to select the speed of the spi. 0 = 30mhz (default) 1 = 60mhz note: if the latched value on reset is 1, this pin is tri-stated when the chip is in the suspend state. if the latched value on reset is 0, this pin is driven low during a suspend state. see note 3.3 for more information on configuration straps. 1 spi data input spi_di is (pd) spi data input table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 17 misc. 1 port 1 over- current sense input ocs1_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condition on usb port 1. 1 port 2 over- current sense input ocs2_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condition on usb port 2. 1 uart receive input uart_rx is internal uart receive input note: this is a 3.3v signal. for rs232 operation, an external 12v translator is required. port 3 over- current sense input ocs3_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condition on usb port 3. 1 uart transmit output uart_tx o8 internal uart transmit output note: this is a 3.3v signal. for rs232 operation, an external 12v driver is required. port 4 over- current sense input ocs4_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condition on usb port 4. 1 system reset input reset_n i_rst this active-low signa l allows exter nal hardware to reset the device. note: the active-low pulse must be at least 5us wide. refer to section 8.4.2, "external chip reset (reset_n)," on page 46 for additional information. 1 crystal input xtal1 iclk external 24 mhz crystal input reference clock input refclk iclk reference clock input. the device may be alternatively driven by a single-ended clock oscillator. when this method is used, xtal2 should be left unconnected. 1 crystal output xtal2 oclk external 24 mhz crystal output 1 external usb transceiver bias resistor rbias ai a 12.0k (+/- 1%) resistor is attached from ground to this pin to set the transceiver?s internal bias settings. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 18 ? 2014 microchip technology inc. 1 suspend output suspend pu this signal is used to indicate that the entire hub has entered the usb suspend state and that vbus current consumption should be reduced in accordance with the usb sp ecification. refer to section 8.6, "suspend (suspend)," on page 47 for additional information. note: suspend must be enabled via the protouch configuration tool. 1 sof synchronized 8khz clock output sof o8 this signal outputs an 8khz clock synchronized with the usb host sof. note: sof output is controlled via the sof_enable bit in the util_config1 register 1 detect upstream vbus power vbus_det is detects state of upstream bus power. when designing a detachable hub, this pin must be connected to the vbus power pin of the upstream usb port through a resistor divider (50k by 100k ) to provide 3.3v. for self-powered applications with a permanently attached host, this pin must be connected to either 3.3v or 5.0v through a resistor divider to provide 3.3v. in embedded applications, vbus_det may be controlled (toggled) when the host desires to renegotiate a connection without requiring a full reset of the device. 1 port 1 power output prtpwr1 o8 enables power to a downstream usb device attached to port 1. 0 = power disabled on downstream port 1 1 = power enabled on downstream port 1 port 1 control prtctl1 od8/is (pu) when configured as prtctl1, this pin functions as both the port 1 power enable output (prtpwr1) and the port 1 over-current sense input (ocs1_n). refer to the prtpwr1 and ocs1_n descriptions for additional information. 1 port 2 power output prtpwr2 o8 enables power to a downstream usb device attached to port 2. 0 = power disabled on downstream port 2 1 = power enabled on downstream port 2 port 2 control prtctl2 od8/is (pu) when configured as prtctl2, this pin functions as both the port 2 power enable output (prtpwr2) and the port 2 over-current sense input (ocs2_n). refer to the prtpwr2 and ocs2_n descriptions for additional information. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 19 1 port 3 power output prtpwr3 o8 enables power to a downstream usb device attached to port 3. 0 = power disabled on downstream port 3 1 = power enabled on downstream port 3 port 3 control prtctl3 od8/is (pu) when configured as prtctl3, this pin functions as both the port 3 power enable output (prtpwr3) and the port 3 over-current sense input (ocs3_n). refer to the prtpwr3 and ocs3_n descriptions for additional information. 1 port 4 power output prtpwr4 o8 enables power to a downstream usb device attached to port 4. 0 = power disabled on downstream port 4 1 = power enabled on downstream port 4 port 4 control prtctl4 od8/is (pu) when configured as prtctl4, this pin functions as both the port 4 power enable output (prtpwr4) and the port 4 over-current sense input (ocs4_n). refer to the prtpwr4 and ocs4_n descriptions for additional information. 6 no connect nc - these pins must be left floating for normal device operation. power 1 battery power supply input vbat p battery power supply input. when vbat is connected directly to a +3.3v supply from the system, the internal +3.3 v regulator runs in dropout and regulator power consumption is eliminated. a 4.7 f (<1 esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4, "power connections," on page 23 for power connection information. 3 +3.3v analog power supply vdda33 p +3.3v analog power supply. a 1.0 f (<1 esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4, "power connections," on page 23 for power connection information. 2 +3.3v power supply vdd33 p +3.3v power supply. these pins must be connected to vdda33. refer to chapter 4, "power connections," on page 23 for power connection information. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 20 ? 2014 microchip technology inc. note 3.2 when the device is configured to enable the hsic upstream port, the usb product id (pid) will be 4604. when the device is conf igured to enable the usb upstream port, the usb pid will be 4504. note 3.3 configuration strap values are latched on power-on reset (por) and the rising edge of reset_n (external chip reset) . configuration straps are id entified by an underlined symbol name. signals that function as co nfiguration straps mu st be augmented with an external resistor when connected to a load. refer to section 6.3, "device configuration straps," on page 32 for additional information. 1 +1.8-3.3v core power supply input vddcorereg p +1.8-3.3v core power supply input to internal +1.2v regulator. this pin may be connected to vdd33 for single supply applications when vbat equals +3.3v. running in a dual supply configuration with vddcorereg at a lower voltage, such as +1.8v, may reduce overall system power consumption. in dual supply configurations, a 4.7 f (<1 esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4, "power connections," on page 23 for power connection information. 1 +1.2v core power supply vddcr12 p +1.2v core power supply. in single supply applications or dual supply applications where 1.2v is not used, a 1.0 f (<1 esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4, "power connections," on page 23 for power connection information. 1 +1.2v hsic power supply input vdd12 p +1.2v hsic power supply input. refer to chapter 4, "power connections," on page 23 for power connection information. exposed pad on package bottom ( figure 3.1 ) ground vss p common ground. this exposed pad must be connected to the ground plane with a via array. table 3.1 pin descriptions (continued) num pins name symbol buffer type description
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 21 3.2 pin assignments table 3.2 48-sqfn package pin assignments pin num pin name pin num pin name 1 vbat 25 spi_ce_n 2 nc 26 spi_do/spi_spd_sel 3 usbdn1_dm/prt_dis_m1 27 spi_clk 4 usbdn1_dp/prt_dis_p1 28 uart_rx/ocs3_n 5 usbdn2_dm/prt_dis_m2 29 prtpwr4/prtctl4 6 usbdn2_dp/prt_dis_p2 30 uart_tx/ocs4_n 7 nc 31 sda/smbdata 8 usbdn3_dm/prt_dis_m3 32 vdd33 9 usbdn3_dp/prt_dis_p3 33 scl/smbclk 10 usbdn4_dm/prt_dis_m4 34 nc 11 usbdn4_dp/prt_dis_p4 35 reset_n 12 vdda33 36 vbus_det 13 sof 37 vdda33 14 suspend 38 vdd12 15 prtpwr1/prtctl1/ 39 flex_hsic_up_strobe 16 ocs1_n 40 flex_usbup_dm/prt_dis_m0 17 vddcr12 41 flex_usbup_dp/prt_dis_p0 18 vdd33 42 flex_hsic_up_data 19 prtpwr2/prtctl2/ 43 xtal2 20 ocs2_n 44 xtal1/refclk 21 prtpwr3/prtctl3 45 nc 22 nc 46 rbias 23 nc 47 vddcorereg 24 spi_di 48 vdda33
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 22 ? 2014 microchip technology inc. 3.3 buffer type descriptions table 3.3 buffer types buffer type description is schmitt-triggered input i_rst reset input i_smb i 2 c/smbus clock input o8 output with 8 ma sink and 8 ma source od8 open-drain output with 8 ma sink o12 output with 12 ma sink and 12 ma source od12 open-drain output with 12 ma sink hsic high-speed inter-chip (hsic) usb specification, version 1.0 compliant input/output pu 50 a (typical) internal pull-up. unless otherwi se noted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. pd 50 a (typical) internal pull-down. unless otherwise noted in the pin description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals ex ternal to the device. when connected to a load that must be pulled low, an external resistor must be added. aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 23 chapter 4 power connections 4.1 integrated power regulators the integrated 3.3v and 1. 2v power regulators provide flexibility to the system in providing power the device. several different configurations are allowed in order to align the power structure to supplies available in the system. the regulators are controlled by reset_n. when reset_n is brought high, the 3.3v regulator will turn on. when reset_n is brought lo w the 3.3v regulator will turn off. 4.1.1 3.3v regulator the device has an integrated regulat or to convert from vbat to 3.3v. 4.1.2 1.2v regulator the device has an integrated regulator to conver t from a variable voltage input on vddcorereg to 1.2v. the 1.2v regulator is tolerant to the pr esence of low voltage (~0v) on the vddcorereg pin in order to support system power so lutions where a supply is not always present in low power states. the 1.2v regulator supports an input voltage range consistent with a 1.8v input in order to reduce power consumption in systems whic h provide multiple power supply levels. in addition, the 1.2v regulator supports an input voltage up to 3.3v for systems which provide only a single power supply. the device will support operation where the 3.3v regulator output can drive the 1.2v regulator input such that vbat is the only required supply. 4.2 power configurations the device supports operation with no back current when power is connected in each of the following configurations. power connection diagrams fo r these configurations are included in section 4.3, "power connection diagrams," on page 25 . 4.2.1 single suppl y configurations 4.2.1.1 vbat only vbat must be tied to the vbat system supply. vdd33, vdda33, and vddcorereg must be tied together on the board. in this configuration t he 3.3v and 1.2v regulators will be active. for hsic operation, vdd12 must be tied to vddcr12. 4.2.1.2 3.3v only vbat must be tied to the 3.3v system supply. vdd33, vdda33, and vddc orereg must be tied together on the board. in this configuration the 3.3v regulator will operate in dropout mode and the 1.2v regulator will be active. for hsic op eration, vdd12 must be tied to vddcr12.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 24 ? 2014 microchip technology inc. 4.2.2 dual supply configurations 4.2.2.1 vbat + 1.8v vbat must be tied to the vbat system supply. vddcorereg must be tied to the 1.8v system supply. in this configuration, the 3.3v regulator and the 1.2v regulator will be active. for hsic operation, vdd12 must be tied to vddcr12. 4.2.2.2 3.3v + 1.8v vbat must be tied to the 3.3v system supply. v ddcorereg must be tied to the 1.8v system supply. in this configuration the 3.3v regulator will o perate in dropout mode and the 1.2v regulator will be active. for hsic operation, vdd12 must be tied to vddcr12.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 25 4.3 power connection diagrams figure 4.1 illustrates the power connections for the usb4 604 with various power supply configurations. note: to achieve the lowest power possible, tie the vdd12 pin to vdd12cr. figure 4.1 power connections hsic 3.3v regulator (in) (out) vbat vbat/+3.3v supply 1.2v core logic 3.3v i/o USB4604 single supply application 1.2v regulator (in) (out) 3.3v internal logic vdda33 (3x) 1.0uf vddcorereg vddcr12 1.0uf vss hsic 3.3v regulator (in) (out) vbat +3.3v supply 1.2v core logic 3.3v i/o USB4604 dual supply application (3.3v & 1.8v) 1.2v regulator (in) (out) 3.3v internal logic 1.0uf vddcorereg vddcr12 1.0uf +1.8v supply vdd33 (2x) hsic only vdda33 (3x) vdd33 (2x) vdd12 vdd12 4.7uf vss 4.7uf 4.7uf hsic only
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 26 ? 2014 microchip technology inc. chapter 5 modes of operation the device provides two main modes of operation: standby mode and hub mode. the operating mode of the device is selected by setting values on primary inputs according to the table below. note: refer to section 8.4.2, "external chip reset (reset_n)," on page 46 for additional information on reset_n. the flowchart in figure 5.1 shows the modes of operation. it also shows how the device traverses through the hub mode stages (shown in bold.) the flow of control is dictated by control register bits shown in italics as well as other events such as availability of a reference clock. the remaining sections in this chapter provide more detail on each stage and mode of operation. table 5.1 controlling modes of operation reset_n input resulting mode summary 0 standby lowest power mode : no functions are active other than monitoring the reset_n input. all port interfaces are high impedance. all regulators are powered off. 1 hub full feature mode : device operates as a configurable usb hub with battery charger detection. power consumption is based on the number of active ports, their speed, and amount of data transferred.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 27 figure 5.1 hub operational mode flowchart yes no combine otp config data soc done? config load from internal rom external spi rom present? yes no run from internal rom run from external spi rom do smbus or i2c initialization sw upstream bc detection (chgdet) hub connect (hub.connect) (config) no (soc_cfg) (sw_init) normal operation smbus or i2c present? yes (hw_init)
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 28 ? 2014 microchip technology inc. 5.1 boot sequence 5.1.1 standby mode if the external hardware reset is asserted, the hub will be in standby mode. this mode provides a very low power state for maximum power efficiency when no signaling is required. this is the lowest power state. in standby mode all internal regulators are po wered off, the pll is not running, and core logic is powered down in order to minimize power cons umption. because core logic is powered off, no configuration settings are retained in this mode and must be re-initialized after reset_n is negated high. 5.1.2 hardware initialization stage (hw_init) the first stage is the initialization stage and occu rs on the negation of reset_n. in this stage the 1.2v regulator is enabled and stabi lizes, internal logic is reset, and the pll locks if a valid refclk is supplied. configuration registers are initialized to their default state and strap input values are latched. the device will complete initialization and automatically enter the next stage. because the digital logic within the device is not yet stable, no communication with the device using the smbus is possible. configuration registers are initialized to their default state. if there is a refclk present, the next state is sw_init. 5.1.3 software initialization stage (sw_init) once the hardware is initialized, the firmware can begin to execute. the internal firmware checks for an external spi rom. the firmware looks for an external spi flash device that contains a valid signature of ?2dfu? (device firmware upgrade) begi nning at address 0xfffa. if a valid signature is found, then the external rom is enabled and the c ode execution begins at address 0x0000 in the external spi device. if a valid signature is not fou nd, then execution continues from internal rom. spi roms used with the device must be 1 mbit and support either 30 mhz or 60 mhz. the frequency used is set using the spi_spd_sel configuration strap. both 1- a nd 2-bit spi operation is supported. for optimum throughput, a 2-bit spi rom is reco mmended. both mode 0 and mode 3 spi roms are also supported. refer to section 6.3.2, "spi speed select (spi_spd_sel)," on page 33 for additional information on selection of the spi speed.for all ot her configurations, the firmware checks for the presence of an external i 2 c/smbus. it does this by asserting tw o pull down resistors on the data and clock lines of the bus. the pull downs are typically 50kohm. if there are 10kohm pull-ups present, the device becomes aware of the presence of an external smbus/i 2 c bus. if a bus is detected, the firmware transitions to the soc_cfg state. 5.1.4 soc configurat ion stage (soc_cfg) in this stage, the soc may modify any of the default co nfiguration settings specified in the integrated rom such as usb device descriptors, or port elec trical settings, and control features such as upstream battery charging detection. there is no time limit. in this stage the firmware will wait indefinitely for the smbus/i 2 c configuration. when the soc has completed configuring the device, it must write to register 0xff to end the configuration. 5.1.5 configuration stage (config) once the soc has indicated that it is done with configuration, then all the configuration data is combined. the default data, the soc configuration data, the otp data are all combined in the firmware and device is programmed.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 29 after the device is fully configured, it will go id le and then into suspend if there is no vbus or hub.connect present. once vbus is present, and upstream battery charging is enabled, the device will transition to the battery charger detection stage (chgdet). if vbus is present, and upstream battery charging is not enabled, the device will transitions to the connect (hub.connect) stage. 5.1.6 battery charger detection stage (chgdet) after configuration, if enabled, the device enters the battery charger detection stage. if the battery charger detection feature was disabled during the config stage, the device will immediately transition to the hub connect (hub.connect) stage. if the battery charger detection feature remains enabled, the battery charger detectio n sequence is started automatically. if the charger detection remains enabled, the device will transition to the hub.connect stage if using the hardware detection mechanism. 5.1.7 hub connect stage (hub.connect) once the chgdet stage is completed, the device enters the hub.connect stage. 5.1.8 normal mode lastly the soc enters the normal mode of operation. in this stage, full usb operation is supported under control of the usb host on the upstream port . the device will remain in the normal mode until the operating mode is c hanged by the system. if reset_n is asserted low, then standby mode is entered. the device may then be placed into any of the designated hub stages. asserting the soft di sconnect on the upstream port will cause the hub to return to the hub.connect stage until the soft disconnect is negated. to save power, communication over the smbus is not supported while in usb suspend. the system can prevent the device from going to sleep by asserting the clksusp control bit of the configure portable hub register anytime before entering usb suspend. while the device is kept awake during usb suspend, it will provide the smbus functionality at the expense of not meeting usb requirements for average suspend current consumption.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 30 ? 2014 microchip technology inc. chapter 6 device configuration the device supports a large number of features (s ome mutually exclusive), and must be configured in order to correctly function when attached to a usb host controller. the hub can be configured either internally or externally dependi ng on the implemented interface. microchip provides a comprehensive software programming tool, pro-touch, for configuring the USB4604 functions, registers and otp memory. all configuration is to be performed via the pro-touch programming tool. for additional information on t he pro-touch programming tool, contact your local microchip sales representative. 6.1 configuration method selection the hub will interface to external memory depending on the configuration of th e device pins associated with each interface type. the device will first check whether an external spi ro m is present. if present, the device will operate entirely from the external rom. when an external spi rom is not present, the device will check whether the smbus is configured. when the smbus is enabled, it can be used to configure the internal device registers via the xdat a address space, or to program the internal otp memory. if no external options are detected, the device will operate using the internal default and configuration strap settings. the order in which devic e configuration is attempted is summarized below: 1. spi (reading the configuration from an spi rom) 2. smbus (either writing the configuration regist ers in the xdata address space, or to otp) 3. internal defaul t settings (with or without configurat ion strap over-rides) note: refer to chapter 7, "device interfaces," on page 34 for detailed information on each device configuration interface. 6.2 customer accessible functions the following usb or smbus accessible functions ar e available to the customer via the pro-touch programming tool. note: for additional programming details, refer to the pro-touch programming tool user manual. 6.2.1 usb accessible functions 6.2.1.1 vsm commands over usb by default, vendor specific messaging (vsm) commands to the hub are enabled. the supported commands are: ? enable embedded controller ? disable embedded controller ? enable special resume ? disable special resume ? reset hub
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 31 6.2.1.2 i 2 c master access over usb access to i 2 c devices is performed as a pass-through operation from the usb host. the device firmware has no knowledge of the operation of the attached i 2 c device. the supported commands are: ? enable i 2 c pass through mode ? disable i 2 c pass through mode ? i 2 c write ? i 2 c read ? send i 2 c start ? send i 2 c stop 6.2.1.3 spi access over usb access to an attached spi device is performed as a pass-through operation from the usb host. the device firmware has no knowledge of the operation of the attached spi device. the supported commands are: ? enable spi pass through mode ? disable spi pass through mode ? spi write ? spi read note: refer to section 7.1, "spi interface," on page 34 for additional information on the spi interface. 6.2.1.4 otp access over usb the otp rom in the device is accessible via the usb bus. all otp parameters can modified via the usb host. the otp operates in single ended mode. the supported commands are: ? enable otp reset ? set otp operating mode ? set otp read mode ? program otp ? get otp status ? program otp control parameters 6.2.1.5 battery charging access over usb the battery charging behavior of the device can be dynamically changed by the usb host when something other than the preprogrammed or otp programmed behavior is desired. the supported commands are: ? enable/disable battery charging ? upstream battery charging mode control ? downstream battery charging mode control ? battery charging timing parameters ? download custom battery charging algorithm
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 32 ? 2014 microchip technology inc. 6.2.1.6 other embedded controller functions over usb the following miscellaneous functions may be configured via usb: ? enable/disable embedded controller enumeration ? program configuration parameters. ? program descriptor fields: ?language id ?manufacturer string ?product string ?idvendor ?idproduct ?bcddevice 6.2.2 smbus accessible functions 6.2.2.1 otp access over smbus the device?s otp rom is accessible over smbus. all otp parameters can modified via the smbus host. the otp can be programmed to operate in si ngle-ended, differential, redundant, or differential redundant mode, depending on the level of reli ability required. the su pported commands are: ? enable otp reset ? set otp operating mode ? set otp read mode ? program otp ? get otp status ? program otp control parameters 6.2.2.2 configuration access over smbus the following functions are available over smbu s prior to the hub attaching to the usb host: ? program configuration parameters. ? program descriptor fields: ?language id ?manufacturer string ?product string ?idvendor ?idproduct ?bcddevice ? program control register 6.3 device configuration straps configuration straps are multi-func tion pins that are driven as outpu ts during normal operation. during a power-on reset (por) or an external chip reset (reset_n) , these outputs are tri-stated. the high or low state of the signal is latched following de -assertion of the reset and is used to determine the default configuration of a particul ar feature. configuration straps are latched as a result of a power-on reset (por) or a external chip reset (reset_n) . configuration strap signals are noted in chapter 3,
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 33 "pin descriptions," on page 11 and are identified by an underl ined symbol name. the following sub- sections detail the various configuration straps. configuration straps include internal resistors in order to prevent the signal from floating when unconnected. if a particular configur ation strap is connected to a load, an external pull-up or pull-down should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be overridden by the addition of an external resistor. note: the system designer must guarantee that c onfiguration straps meet the timing requirements specified in section 9.5.2, "reset and configuration strap timing," on page 54 and section 9.5.1, "power-on conf iguration strap valid timing," on page 54 . if configuration straps are not at the correct voltage level prior to being la tched, the device may capture incorrect strap values. note: configuration straps must never be driven as inputs. if required, configuration straps can be augmented, or overridden with external resistors. 6.3.1 port disable (prt_dis_m x /prt_dis_p x ) these configuration straps disabl e the associated usb ports d- and d+ signals, respectively, where ? x ? is the usb port number. both the negative ?m? and po sitive ?p? port disable configuration straps for a given usb port must be tied high at reset to disable the associated port. 6.3.2 spi speed select (spi_spd_sel ) this strap is used to select the speed of the spi as follows: note: if the latched value on reset is 1, this pin is tri-stated when the chip is in the suspend state. if the latched value on reset is 0, this pin is driven low during a suspend state. table 6.1 prt_dis_m x /prt_dis_p x configuration definitions prt_dis_m x /prt_dis_p x definition ?0? port x d-/d+ signal is enabled (default) ?1? port x d-/d+ signal is disabled table 6.2 spi_spd_sel configuration definitions spi_spd_sel definition ?0? 30 mhz spi operation (default) ?1? 60 mhz spi operation
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 34 ? 2014 microchip technology inc. chapter 7 device interfaces the USB4604 provides multiple interfaces for conf iguration and external memory access. this chapter details the various device interfaces and their usage. note: for information on device configuration, refer to chapter 6, "device conf iguration," on page 30 . 7.1 spi interface the device is capable of code exec ution from an external spi rom. on power up, the firmware looks for an external spi flash device that contains a valid signature of 2dfu (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the external rom is enabled and the code execution begins at address 0x0000 in the exte rnal spi device. if a valid signature is not found, then execution continues from inte rnal rom. the following sections describe the interface options to the external spi rom. the spi interface is always enabled after reset. it can be disabled by setting the spi_disable bit in the util_config1 register. note: for spi timing info rmation, refer to section 9.5.7, "spi timing," on page 56 . 7.1.1 operation of the hi-speed read sequence the spi controller will automatically handle code reads going out to the spi rom address. when the controller detects a read, the controller drives spi_ce_n low, and outputs 0x0b, followed by the 24- bit address. the spi controller outputs a dummy byte. the next eight clocks will clock-in the first byte. when the first byte is clocked-in, a ready signal is sent back to the processor, and the processor gets one byte. after the processor gets the first byte, its address will change. if the address is one more than the last address, the spi controller will clock out one more byte. if the address is anything other than one more than the last address, the spi controller will termi nate the transaction by driving spi_ce_n high. as long as the addresses are sequential, the spi controller will continue clocking data in. figure 7.1 spi hi-speed read sequence spi_ce_n spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d out add. 23 24 add. add. x 39 40 31 32 47 48 55 56 63 64 71 72 80 d out nn+1 d out n+2 d out n+3 d out n+4 msb msb
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 35 7.1.2 operation of the dual high speed read sequence the spi controller also supports dual data mode. when configured in dual mode, the spi controller will automatically handle xdata reads going out to the spi rom. when the controller detects a read, the controller drives spi_ce_n low and outputs 0x 3b (the value must be programmed into the spi_ fr_opcode register) followed by the 24 bit address. bits 23 through bit 17 are forced to zero, and address bits 16 through 0 are directly from the xd ata address bus. because it is in fast read mode, the spi controller then outputs a du mmy byte. the next four clocks will clock-in the first byte. the data appears two bits at a time on spi_do and spi _di. when the first byte is clocked in, a ready signal is sent back to the processor, and the processor gets one byte. after the processor gets the first byte, its address will change. if the address is one more than the last address, the spi controller will clock out one more by te. if the address in anything other than one more than the last address, the spi controller will termi nate the transaction by driving spi_ce_n high. as long as the addresses are sequential, the spi controller will continue clocking data in. 7.1.3 32 byte cache there is a 32-byte pipeline cache with an associat ed base address pointer and length pointer. once the spi controller detects a jump, the base address poi nter is initialized to that address. as each new sequential data byte is fetched, th e data is written into the cache and the length is incr emented. if the sequential run exceeds 32 bytes, the base address poi nter is incremented to indi cate the last 32 bytes fetched. if the firmware performs a jump, and the ju mp is in the cache address range, the fetch is done in 1 clock from the internal ca che instead of an external access. 7.1.4 interface operation to the spi port when not performing fast reads there is a 8-byte command buffer (spi_cmd_buf[7:0]), an 8-byte response buffer (spi_resp_buf[7:0]), and a length register that counts out the number of bytes (spi_cmd_len). additionally, there is a self-clearing go bit in t he spi_ctl register. once the go bit is set, device drives spi_ce_n low and starts clocking. it will then output spi_cmd_len x 8 number of clocks. after the first command byte has been se nt out, the spi_di inpu t is stored in the spi_resp buffer. if the spi_cmd_len is longer than the spi_cmd_buf, do n?t cares are sent out on the spi_do output. this mode is used for program exec ution out of internal ram or rom. figure 7.2 spi dual hi-speed read sequence spi_ce_n spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d1 add. 23 24 add. add. x 39 40 31 32 44 47 48 51 52 55 56 59 d2 nn+1 d3 n+2 d4 n+3 d5 n+4 msb msb d1 d2 n n+1 d3 n+2 d4 n+3 d5 n+4 msb 43 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-7,5,3,1 bits-6,4,2,0
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 36 ? 2014 microchip technology inc. automatic reads and writes happen when there is an external xdata read or write, using the serial stream that has been previously discussed. 7.1.5 erase example to perform a sctr_erase, 32blk_erase, or 64bl k_erase, the device writes 0x20, 0x52, or 0xd8, respectively to the first byte of the comm and buffer, followed by a 3-byte address. the length of the transfer is set to 4 bytes. to perform this , the device drives spi_ce_n low, then counts out 8 clocks. it then outputs on spi_do the 8 bits of comm and, followed by 24 bits of address of the location to be erased. when the transfer is complete, spi_ ce_n goes high, while the spi_di line is ignored in this example. figure 7.3 spi erase sequence spi_ce_n spi_clk 16 23 24 31 15 123 4 05 7 6 add. spi_do spi_di 8 command msb msb add. add. high impedance
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 37 7.1.6 byte program example to perform a byte program, the device writes 0x02 to the first byte of the command buffer, followed by a 3-byte address of the location that will be writ ten to, and one data byte. the length of the transfer is set to 5 bytes. the device first drives spi_c e_n low, then spi_do outputs 8 bits of command, followed by 24 bits of address, and one byte of data. spi_di is not used in this example. figure 7.4 spi byte program sequence spi_ce_n spi_clk 16 23 24 31 15 39 123 4 05 7 6 0x00 spi_do spi_di 8 0xdb msb msb 0xfe /0xff data msb lsb 32 high impedance 0xbf
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 38 ? 2014 microchip technology inc. 7.1.7 command only program example to perform a single byte command such as the following: - wrdi - wren - ewsr - chip_erase - ebsy - dbsy the device writes the opcode into the first by te of the spi_cmd_buf and the spi_cmd_len is set to one. the device first drives spi_ce_n low, then 8 bits of the command are clocked out on spi_do. spi_di is not used in this example. figure 7.5 spi command only sequence spi_ce_n spi_clk 1234 057 6 spi_do spi_di command msb high impedance
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 39 7.1.8 jedec-id read example to perform a jedec-id command, the device writes 0x9f into the first byte of the spi_cmd_buf. the length of the transfer is 4 bytes. the devic e first drives spi_ce_n low, then spi_do is output with 8 bits of the command, followed by the 24 bits of dummy bytes (due to the length being set to 4). when the transfer is complete, spi_ce_n goes high. after the first byte, the data on spi_di is clocked into the spi_rsp_buf. at the end of the command, there are three valid bytes in the spi_rsp_buf. in this example, 0xbf, 0x25, 0x8e. 7.2 i 2 c master interface the i 2 c master interface implements a subset of the i 2 c master specification (please refer to the philips semiconductor standard i 2 c-bus specification for details on i 2 c bus protocols). the device?s i 2 c master interface conforms to the standard-mode i 2 c specification (100 kbit/s transfer rate and 7- bit addressing) for protocol and electrical compatib ility. the device acts as the master and generates the serial clock scl, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the start and stop conditions. note: extensions to the i 2 c specification are not supported. note: all device configuration must be performed via the pro-touch programming tool. for additional information on the pro-touch programming tool , contact your local sales representative. 7.2.1 i 2 c message format 7.2.1.1 sequential access writes the i 2 c interface supports sequential writing of the device?s register address space. this mode is useful for configuring conti guous blocks of registers. figure 7.7 shows the format of the sequential figure 7.6 spi jedec-id read sequence spi_ce_n spi_clk spi_do spi_di 8 9f msb high impedance 11 12 13 14 15 16 123 4 05 7 6 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bf 25 8e msb msb
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 40 ? 2014 microchip technology inc. write operation. where color is visible in t he figure, blue indicates signaling from the i 2 c master, and gray indicates signaling from the slave. in this operation, following the 7-bit slave address, the 8-bit register address is written indicating the start address for sequential write operation. every s ubsequent access is a data write to a data register, where the register address increments after each access and an ack from the slave occurs. sequential write access is te rminated by a stop condition. 7.2.1.2 sequential access reads the i 2 c interface supports direct reading of the device re gisters. in order to read one or more register addresses, the starting address must be set by us ing a write sequence followed by a read. the read register interface supports auto-i ncrement mode. the master must send a nack instead of an ack when the last byte has been transferred. in this operation, following the 7-bit slave address, the 8-bit register address is written indicating the start address for the subsequent sequential read oper ation. in the read sequence, every data access is a data read from a data register where the regi ster address increments after each access. the write sequence can end with optional stop (p). if so, the read sequence must begin with a start (s). otherwise, the read sequence must start with a repeated start (sr). figure 7.8 shows the format of the read operation. wher e color is visible in the figure, blue and gold indicate signaling from the i 2 c master, and gray indicates signaling from the slave. figure 7.7 i 2 c sequential access write format figure 7.8 i 2 c sequential access read format s 7-bit slave address 0 p a nnnnnnnn data value for xxxxxx ... nnnnnnnn a data value for xxxxxx + y a xxxxxxxx a register address (bits 7-0) s 7-bit slave address 1 n n n n n n n n p ack ack register value for xxxxxxxx n n n n n n n n ack register value for xxxxxxxx + 1 ... n n n n n n n n nack if previous write setting up register address ended with a stop (p), otherwise it will be repeated start (sr) register value for xxxxxxxx + y s 7-bit slave address 0 p a xxxxxxxx a register address (bits 7-0) optional. if present, next access must have start(s), otherwise repeat start (sr)
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 41 7.2.2 pull-up resistors for i 2 c the circuit board designer is required to place external pull-up resistors (10 k recommended) on the sda & scl signals (per smbus 1.0 specification) to vcc in order to assure proper operation. 7.3 smbus slave interface the USB4604 includes an integrated smbus slave interface, which can be used to access internal device run time registers or program the internal otp memory. smbus detection is accomplished by detection of pull-up resistors (10 k recommended) on both the smbdata and smbclk signals. to disable the smbus, a pull-down resistor of 10 k must be applied to smbd ata. the smbus interface can be used to configure the device as detailed in section 6.1, "configuration method selection," on page 30 . note: all device configuration must be performed via the pro-touch programming tool. for additional information on the pro-touch programming tool, contact your local microchip sales representative.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 42 ? 2014 microchip technology inc. chapter 8 functional descriptions this chapter provides additional function al descriptions of key device features. 8.1 battery charger detection & charging the USB4604 supports both upstream battery charger detection and downstream battery charging. the integrated battery charger detection circuitr y supports the usb-if battery charging (bc1.2) detection method and most apple devices. these ci rcuits are used to detect the attachment and type of a usb charger and provide an in terrupt output to indicate charger information is available to be read from the device?s status registers via the serial in terface. the USB4604 provides the battery charging handshake and supports the following usb-if bc1.2 charging profiles: ? dcp: dedicated charging port (power brick with no data) ? cdp: charging downstream port (1.5a with data) ? sdp: standard downstream port (0.5a with data) ? custom profiles loaded via smbus or otp the following sub-sections detail the upstream battery charger detection and downstream battery charging features. 8.1.1 upstream battery charger detection battery charger detection is available on the upstre am facing port. the detection sequence is intended to identify chargers which confor m to the chinese battery charger specification, chargers which conform to the usb-if battery charger sp ecification 1.2, and most apple devices. in order to detect the charger, the device applies and monitors voltages on the upstream dp and dm pins. if a voltage within the specif ied range is detected, the device will be updated to reflect the proper status. the device includes the circuitry required to impl ement battery charging dete ction using the battery charging specification. when enabled, the device will automatically perform charger detection upon entering the hub.chgdet stage in hub mode. the dev ice includes a state machine to provide the detection of the usb chargers listed in the table below. table 8.1 chargers compatible with upstream detection usb attach type dp/dm profile chargertype dcp (dedicated charging port) shorted < 200ohm 001 cdp (charging downstream port) vdp reflected to vdm 010 (enhancedchrgdet = 1) sdp (standard downstream port) usb host or downstream hub port 15kohm pull-down on dp and dm 011 apple low current charger apple 100 apple high current charger apple 101 apple super high current charger dp=2.7v dm=2.0v 110
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 43 if a custom charger detection algor ithm is desired, the smbus registers can also be used to control the charger detection block to implement a custom charger detection algorithm. in order to avoid negative interactions with automatic battery charger detection or normal hub operation, the user should only attempt custom battery charger detection duri ng the hub.config stage or hub.connect stage. no logic is implemented to disable custom detection at othe r times - it is up to the user software to observe this restriction. there is a possibility that the system is not runnin g the reference clock when battery charger detection is required (for example if the battery is dead or missing). during the hub.wait refclk stage the battery charger detection sequence can be configured to be followed regardless of the activity of refclk by relying on the operation of the internal oscillator. note: battery charger detection is not available when utilizing hsic on the upstream port. 8.1.2 downstream battery charging the device can be configured by an oem to have any of the downstream ports to support battery charging. the hub's role in battery charging is to provide an acknowledge to a device's query as to if the hub system supports usb battery charging. the hub silicon does not provide any current or power fets or any additional circuitry to actually charge the device. those components must be provided as externally by the oem. if the oem provides an external supply capabl e of supplying current per the battery charging specification, the hub can be configured to indicate the presence of such a supply to the device. this indication, via the prtpwr[1:4] output pins, is on a per/port basis. for example, the oem can configure two ports to support battery charging through high current power fet's and leave the other two ports as standard usb ports. note: battery charging is not available on downstream hsic ports. apple charger low current charger (500ma) dp=2.0v dm=2.0v 100 apple charger high current charger (1000ma) dp=2.0v dm=2.7v 101 figure 8.1 battery charging external power supply table 8.1 chargers compatible wi th upstream detection (continued) usb attach type dp/dm profile chargertype soc vbus[n] prtpwr[n] int scl sda microchip hub dc power
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 44 ? 2014 microchip technology inc. 8.1.2.1 downstream battery charging modes in the terminology of the usb battery charging specif ication, if a port is configured to support battery charging, the downstream port is a considered a cdp (charging downstream port) if connected to a usb host, or a dcp (dedicated charging port) if not connected to a usb host. if the port is not configured to support battery charging, the port is considered an sdp (standard downstream port). all charging ports have electrical characteri stics different from standard non-charging ports. a downstream port will behave as a cdp, dcp, or sdp depending on the port?s configuration and mode of operation. the port will not switch between a cdp/dcp or sdp at any time after initial power- up and configuration. a downstream port can be in one of three modes shown in the table below. 8.1.2.2 downstream batter y charging configuration configuration of ports to supp ort battery charging is perform ed via usb configuration, smbus configuration, or otp. the battery charging enab le register provides per port battery charging configuration. starting from bit 1, this register e nables battery charging for each down stream port when asserted. bit 1 represents port 1 and so on. each port with battery charging enabled asserts the corresponding prtpwr register bit. 8.1.2.3 downstream over -current management it is the devices responsibility to manage over-c urrent conditions. over-c urrent sense (ocs) is handled according to the usb specification. for battery charging ports, prtpwr is driven high (asserted) after hardware initializ ation. if an ocs event occurs, the prtpwr is negated. prtpwr will be negated for all ports in a ganged configuratio n. only the respective prtpwr will be negated in the individual configuration. if there is an over-curre nt event in dcp mode, the port is turn ed off for one second and is then re- enabled. if the ocs event persists, the cycle is r epeated for a total or three times. if after three attempts, the ocs still persi sts, the cycle is still repe ated, but with a retry inte rval of ten seconds. this retry persists for indefinitely. the indefinite retry prevents a defective device from permanently disabling the port. in cdp or sdp mode, the port power and over-current events are controlled by the usb host. the ocs event does not have to be regi stered. when and if the hub is connected to a host, the host will initialize the hub and enable its port power. if the over current still exists, it will be notified at that point. table 8.2 downstream port types usb attach type dp/dm profile dcp (dedicated charging port) apple charging mode or china mode (shorted < 200ohm) or mchp custom mode cdp (charging downstream port) vdp reflected to vdm sdp (standard downstream port) usb host or downstream hub port 15kohm pull-down on dp and dm
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 45 8.2 sof clock output the USB4604 provides an 8khz clock output synchro nized to the usb host sofs. the sof output is generated from the previous sof packet on the usb lin e. the device includes an internal free running frame counter to generate internal start of frame and end of frame events. the internal counter is re- synchronized every time a succes sful packet is received and decoded. the internal counter is advanced to compensate for the packet decode time. if the incoming sof jitters early or late, the jitter will be visible in the next frame sof output clock rising edge. if one or two sofs are missing, the sof output will continue based on the internal frame counter. if more than two sof are missing, t he sof output signal will stop. the clock is guaranteed to stop in a low state. when enabled or disabled, there will never be a short cycle. figure 8.2 sof output timing 8.3 flex connect this feature allows the upstream port to be swapped with downstream physical port 1. only downstream port 1 can be swapped physically. usin g port remapping, any logical port (number assignment) can be swapped with t he upstream port (non-physical). flex connect is enabled/disabled via two control bi ts in the connect configuration register. the flexconnect configuration bit switches the port, and en_flex_mode enables the mode. 8.3.1 port control once en_flex_mode bit is set, the functions of certain pins change, as outlined below. if en_flex_mode is set and flexconnect is not set: 1. prtpwr1 enters combined mo de, becoming prtpwr1/ocs1_n 2. ocs1_n becomes a don?t care 3. suspend outputs ?0? to keep any upstream power controller off if en_flex_mode is set and flexconnect is set: 1. the normal upstream vbus pin becomes a don?t care 2. prtpwr1 is forced to a ?1? in combined mode, keeping the port power on to the application processor. 3. ocs1 becomes vbus from the app lication processor through a gpio 4. suspend becomes prtpwr1/ocs1_n for the port power controller for the connector port upstream hs usb internal frame counter events sof (khz) sof packet accepted eof1 eof2 sof sof packet accepted eof1 eof2 sof
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 46 ? 2014 microchip technology inc. 8.4 resets the device has the followin g chip level reset sources: ? power-on reset (por) ? external chip reset (reset_n) ? usb bus reset 8.4.1 power-on reset (por) a power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the device. a timer within the device will assert the internal reset per the specifications listed in section 9.5.1, "power-o n configuration strap valid timing," on page 54 . 8.4.2 external chip reset (reset_n) a valid hardware reset is defined as assertion of reset_n, after all power supplies are within operating range, per the specifications in section 9.5.2, "reset and c onfiguration strap timing," on page 54 . while reset is asserted, the de vice (and its associated external circuitry) enters standby mode and consumes minimal current. assertion of reset_n causes the following: 1. the phy is disabled and the differential pairs will be in a high-impedance state. 2. all transactions immediately terminate; no states are saved. 3. all internal registers return to the default state. 4. the external crystal oscillator is halted. 5. the pll is halted. 6. the hsic strobe and data pins are driven low. note: all power supplies must have reached the operating levels mandated in section 9.2, "operating conditions**," on page 49 , prior to (or coincident with ) the assertion of reset_n. 8.4.3 usb bus reset in response to the upstream port signaling a rese t to the device, the devi ce performs the following: note: the device does not propagate the upstream usb reset to downstream devices. 1. sets default address to 0. 2. sets configuration to: unconfigured. 3. moves device from suspended to active (if suspended). 4. complies with section 11.10 of the usb 2.0 s pecification for behavior after completion of the reset sequence. the host then configures the device in accordance with t he usb specification. 8.5 link power management (lpm) the device supports the l0 (on), l1 (sleep), and l2 (suspend) link power management states per the usb 2.0 link power management addendum. thes e supported lpm states offer low transitional
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 47 latencies in the tens of microseconds versus the much longer latencies of the traditional usb suspend/resume in the tens of milliseconds . the supported lpm states are detailed in table 8.3 . for additional information, refer to the u sb 2.0 link power management addendum. note: state change timing is approximate and is measured by change in power consumption. note: system clocks are stopped only in suspend mo de or when power is removed from the device. 8.6 suspend (suspend) when enabled, the suspend signal can be used to indicate that the entire hub has entered the usb suspend state and that vbus current consumptio n should be reduced in accordance with the usb specification. selective suspend set by the host on dow nstream hub ports have no effect on this signal because there is no requirement to reduce curren t consumption from the upstream vbus. suspend can be used by the system to moni tor and dynamically adjust how much current the pmic draws from vbus to charge the battery in the system during a usb session. because it is a level indication, it will assert or negate to reflect the current status of suspend without any interaction through the smbus. a negation of this signal indicates no level suspend interrupt and device has been configured by the usb host. the full configured current can be dr awn from the usb vbus pin on the usb connector for charging - up to 500ma - depending on descriptor settings. when asserted, this signal indicates a suspend interrupt or that the device has not yet been configured by usb host. the current draw can be limited by the system according to the usb specificat ion. the usb specification limits current to 100ma before configuration, and up to 12.5ma in usb suspend mode. table 8.3 lpm state definitions state description entry/exit time to l0 l2 suspend entry: ~3 ms exit: ~2 ms l1 sleep entry: ~65 us exit: ~100 us l0 fully enabled (on) -
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 48 ? 2014 microchip technology inc. chapter 9 operational characteristics 9.1 absolute maximum ratings* vbat supply voltage ( note 9.1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +5.5 v vddcorereg supply voltage ( note 9.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +3.6 v , positive voltage on input signal pins, with respect to ground ( note 9.2 ) . . . . . . . . . . . . . . . . . . . 3.6 v negative voltage on input signal pins, with respect to ground ( note 9.3 ). . . . . . . . . . . . . . . . . . . -0.5 v positive voltage on xtal1/refclk, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . .vddcr12 positive voltage on hsic signals, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32 v positive voltage on usb dp/dm signals, with respect to ground ( note 9.4 ) . . . . . . . . . . . . . . . . . 5.5 v storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .jedec class 3a note 9.1 when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested to use a clamp circuit. note 9.2 this rating does not apply to the followi ng signals: all usb dm/dp pins, xtal1/refclk, xtal2, and all hsic signals. note 9.3 this rating does not apply to the hsic signals. note 9.4 this rating applies only when vdd33 is powered. *stresses exceeding those listed in this section c ould cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 9.2, "operating conditions**" , section 9.4, "dc specifications" , or any other applicable section of this specification is not implied. note, device signals are not 5 volt tolerant unless specified otherwise.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 49 9.2 operating conditions** vbat supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to +5.5 v vddcorereg supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 9.5 power supply rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 9.6 ambient operating temperature in still air (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 9.7 note 9.5 +1.6 v to +2.0 v when vddcorereg is connected to an external +1.8v power supply, +3.0 v to +3.6 v when vddcorereg is connected to vdd33. note 9.6 the power supply rise time requirements vary dependent on the usage of the external reset (reset_n). if reset_n is asserted at power-on, the power supply rise time must be 10ms or less (t rt(max) = 10ms). if reset_n is not used at power-on (tied high), the power supply rise time must be 1ms or less (t rt(max) = 1ms). higher voltage supplies must always be at an equal or higher voltage than lower voltage supplies. figure 9.1 illustrates the supply rise time requirements. note 9.7 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. **proper operation of the device is guaranteed on ly within the ranges specified in this section. figure 9.1 single/dual supply rise time models t 10% 10% 90% voltage t rt t 90% time 100% 3.3v/vbat vss vbat t 10% 10% 90% voltage t rt t 90% time 100% 3.3v vss vbat 90% 100% 1.8v vddcorereg single supply rise time model dual supply rise time model
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 50 ? 2014 microchip technology inc. 9.3 power consumption this section details the power consumption of the device as measured during various modes of operation. power dissipation is determined by temper ature, supply voltage, and external source/sink requirements. 9.3.1 operational / unconfigured 9.3.1.1 hsic upstream note 9.8 includes vdd12 current. 9.3.1.2 usb upstream table 9.1 operational/unconfigured power consumption (hsic upstream) typical (ma) maximum (ma) vbat vddcorereg ( note 9.8 ) vbat vddcorereg ( note 9.8 ) hs host / 1 hs device 30 40 35 45 hs host / 2 hs devices 50 50 60 55 hs host / 4 hs devices 90 60 100 70 hs host / 1 fs device 15 30 20 40 hs host / 2 fs devices 20 35 20 45 hs host / 4 fs devices 20 40 25 50 unconfigured 10 20 - - table 9.2 operational/unconfigured power consumption (usb upstream) typical (ma) maximum (ma) vbat vddcorereg vbat vddcorereg hs host / 1 hs device 30 40 40 45 hs host / 2 hs devices 55 50 65 55 hs host / 4 hs devices 100 65 105 75 hs host / 1 fs device 20 30 25 40 hs host / 2 fs devices 20 40 30 40 hs host / 4 fs devices 25 40 30 45 unconfigured 10 20 - -
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 51 note 9.9 includes vdd12 current. 9.3.2 suspend / standby 9.3.2.1 single supply the following tables detail the device power consumption when configured with a single vbat supply and an externally supplied vdd12 for hsic (when applicable) for additional information on power connections, refer to chapter 4, "power connections," on page 23 . 9.3.2.1.1 usb upstream note: typical values measured with vbat = 4.2v. maximum values measured with vbat = 5.5v. 9.3.2.1.2 hsic upstream note: typical values measured with vbat = 4.2v, vdd12 = 1.2v. maximum values measured with vbat = 5.5v, vdd12 = 1.32v. table 9.3 single supply suspend/stan dby power consumption (usb upstream) mode symbol typical @ 25 o ccommercial max industrial max unit suspend i vbat 320 1200 2000 ua standby i vbat 0.4 2.0 2.4 ua table 9.4 single supply suspend/standby power consumption (hsic upstream) mode symbol typical @ 25 o ccommercial max industrial max unit suspend i vbat 120 1200 1500 ua i vdd12 5 550 750 ua standby i vbat 0.2 1.9 2.2 ua
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 52 ? 2014 microchip technology inc. 9.3.2.2 dual supply the following tables detail the device power consum ption when configured with a dual supply (vbat and 1.8v vddcorereg) and an externally supplied vdd12 for hsic (when applicable) for additional information on power connections, refer to chapter 4, "power connections," on page 23 . 9.3.2.2.1 usb upstream note: typical values measured with vbat = 4.2v, vddcorereg = 1.8v. maximum values measured with vbat = 5.5v, vddcorereg = 2.0v. 9.3.2.2.2 hsic upstream note: typical values measured with vbat = 4.2v, vddcorereg = 1.8v, vdd12 = 1.2v. maximum values measured with vbat = 5.5v, vddcorereg = 2.0v, vdd12 = 1.32v. table 9.5 dual supply suspend/standby power consumption (usb upstream) mode symbol typical @ 25 o ccommercial max industrial max unit suspend i vddcorereg 80 900 1350 ua i vbat 230 400 400 ua standby i vddcorereg 0.1 1.2 2.5 ua i vbat 0.4 2.1 2.5 ua table 9.6 dual supply suspend/standby power consumption (usb upstream) mode symbol typical @ 25 o ccommercial max industrial max unit suspend i vddcorereg 90 900 1300 ua i vbat 30 500 750 ua i vdd12 5.5 650 1100 ua standby i vddcorereg 0.1 1.2 2.5 ua i vbat 0.4 2.1 2.5 ua
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 53 9.4 dc specifications table 9.7 dc electrical characteristics parameter symbol min typ max units notes is type input buffer low input level high input level v il v ih -0.3 2.0 0.8 3.6 v v i_rst type input buffer low input level high input level v il v ih -0.3 1.25 0.4 3.6 v v i_smb type input buffer low input level high input level v il v ih -0.3 1.25 0.35 3.6 v v o8 type buffers low output level high output level v ol v oh vdd33 - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma od8 type buffer low output level v ol 0.4 v i ol = 8 ma o12 type buffers low output level high output level v ol v oh vdd33 - 0.4 0.4 v v i ol = 12 ma i oh = -12 ma od12 type buffer low output level v ol 0.4 v i ol = 12 ma hsic type buffers low input level high input level low output level high output level v il v ih v ol v oh -0.3 0.65*vdd12 0.75*vdd12 0.35*vdd12 vdd12+0.3 0.25*vdd12 v v v v iclk type buffer (xtal1/refclk input) low input level high input level v il v ih -0.3 0.8 0.35 3.6 v v
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 54 ? 2014 microchip technology inc. 9.5 ac specifications this section details the various ac ti ming specifications of the device. 9.5.1 power-on configurat ion strap valid timing figure 9.1 illustrates the configuration strap timing requirements, in relati on to power-on, for applications where reset_n is not used at power-on. the ope rational levels (v opp ) for the external power supplies are detailed in section 9.2, "operating conditions**," on page 49 . note: for reset_n configuration strap timing requirements, refer to section 9.5.2, "reset and configuration strap timing," on page 54 . 9.5.2 reset and configuration strap timing figure 9.2 illustrates the reset_n timing requirements and its relation to the configuration strap signals. assertion of reset_n is not a requirement. howe ver, if used, it must be asserted for the minimum period specified. figure 9.1 power-on configuration strap valid timing table 9.8 power-on configuration strap valid timing symbol description min typ max units t csh configuration strap hold after external power supplies at operational levels 1ms all external power supplies v opp configuration straps t csh
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 55 refer to section 8.4, "resets," on page 46 for additional informati on on resets. refer to section 6.3, "device configuration straps," on page 32 for additional information on configuration straps. 9.5.3 usb timing all device usb signals conform to the voltage, power, and timing characteristi cs/specifications as set forth in the universal serial bus specification . please refer to the universal serial bus specification , revision 2.0, available at http://www.usb.org. 9.5.4 hsic timing all device hsic signals conform to the voltage, powe r, and timing characteristics/specifications as set forth in the high-speed inter-chip usb electrical specification . please refer to the high-speed inter- chip usb electrical specification , version 1.0, available at http://www.usb.org. 9.5.5 smbus timing all device smbus signals conform to the voltage, power, and timing characteri stics/specifications as set forth in the system management bus specification . please refer to the system management bus specification , version 1.0, available at http://smbus.org/specs. 9.5.6 i 2 c timing all device i 2 c signals conform to the 100khz standard mode (sm) voltage, power, and timing characteristics/specificatio ns as set forth in the i 2 c-bus specification . please refer to the i 2 c-bus specification , available at http://www.nxp.com. figure 9.2 reset_n conf iguration strap timing table 9.9 reset_n configuration strap timing symbol description min typ max units t rstia reset_n input assertion time 5 us t csh configuration strap hold af ter reset_n de assertion 1 ms reset_n configuration straps t rstia t csh
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 56 ? 2014 microchip technology inc. 9.5.7 spi timing the following specifies the spi timing requirements for the device. note: the spi can be configured for 30 mhz or 60 mhz operation via the spi_spd_sel configuration strap. 30 mhz operation timing values are shown in table 9.10 . 60 mhz operation timing values are shown in ta b l e 9 . 11 . figure 9.3 spi timing table 9.10 spi timing values (30 mhz operation) symbol description min typ max units t fc clock frequency 30 mhz t ceh chip enable (spi_ce_en) high time 100 ns t clq clock to input data 13 ns t dh input data hold time 0 ns t os output setup time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns t cel chip enable (spi_ce_en) low to first clock 12 ns t ceh last clock to chip enable (spi_ce_en) high 12 ns spi_clk spi_di spi_do spi_ce_n t cel t fc t clq t ceh t dh t oh t os t ov t oh
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 57 9.6 clock specifications the device can accept either a 24 mhz crystal or a 24 mhz single-ended clock oscillator input. if the single-ended clock oscillator method is implemented, xtal1 should be left unconnected and refclk should be driven with a clock that adhe res to the specifications outlined in section 9.6.2, "external reference clock (refclk)" . 9.6.1 oscillator/crystal it is recommended that a crystal utilizing matchi ng parallel load capacitors be used for the crystal input/output signals (xtal1i/xtal2). see ta b l e 9 . 1 2 for the recommended crystal specifications. note 9.10 0 o c for commercial version, -40 o c for industrial version. note 9.11 +70 o c for commercial version, +85 o c for industrial version. table 9.11 spi timing values (60 mhz operation) symbol description min typ max units t fc clock frequency 60 mhz t ceh chip enable (spi_ce_en) high time 50 ns t clq clock to input data 9 ns t dh input data hold time 0 ns t os output setup time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns t cel chip enable (spi_ce_en) low to first clock 12 ns t ceh last clock to chip enable (spi_ce_en) high 12 ns table 9.12 crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 24.000 - mhz total allowable ppm budget - - +/-350 ppm operating temperature range note 9.10 - note 9.11 o c
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 58 ? 2014 microchip technology inc. 9.6.2 external reference clock (refclk) the following input clock specifications are suggested: ? 24 mhz 350 ppm note: the external clock is recommended to conform to the signalling levels designated in the jedec specification on 1.2v cmos logic. xta l2 should be treated as a no connect when an external clock is supplied.
usb 2.0 hsic hi-speed 4-port hub controller datasheet ? 2014 microchip technology inc. ds00001716a-page 59 chapter 10 package outline figure 10.1 48-sqfn package drawing note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
usb 2.0 hsic hi-speed 4-port hub controller datasheet ds00001716a-page 60 ? 2014 microchip technology inc. chapter 11 datasheet revision history table 11.1 revision history revision level & date section/figure/entry correction USB4604 revision a replaces the previous smsc version, revision 1.1 rev. 1.1 (03-06-14) ordering codes, intro added new ?-1070? ordering option and detailed the differences between -1080 and -1070 (hub controller enabled/disabled). rev. 1.1 (12-06-13) smbus runtime registers register definitions removed. these definitions are provided in application note an 26.18 ?smbus slave interface for the usb253x/usb3x13/usb46x4? . rev. 1.1 (09-24-13) table 9.7, ?dc electrical characteristics,? on page 53 updated iclk v ih max from ?vddcr12? to ?3.6? section 9.6.2, "external reference clock (refclk)," on page 58 removed 50% duty cycle requirement. rev. 1.0 (06-17-13) initial release
? 2014 microchip technology inc. ds00001716a-page 61 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digita l millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. information contained in this publication re garding device applications a nd the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liabil ity arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at t he buyer?s risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expe nses resulting from such us e. no licenses are conveyed, implic- itly or otherwise, under any micr ochip intellectual property rights. trademarks the microchip name and logo, the micr ochip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered tr ademarks of microchip technology incorporated in the u.s.a. a nd other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z- scale are trademarks of microc hip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. flexpwr, jukeblox, kleer, kleernet, medialb, and most the preceding is a non-exhaustive list of tra demarks in use in the us and other countri es. for a complete list of trademarks, e mail a request to legal.department@microchip.com . the absence of a trademark (name, logo, etc.) from the list does not constitute a waiver of any intellectual property rights that smsc has established in any of its trademarks. all other trademarks mentioned herein are pr operty of their respective companies. ? 2014, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 9781632760302 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management system certified by dnv == iso/ts 16949 ==
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